Rozhin Yasaei

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Courses

Scholarly Contributions

Chapters

• Olabanjo, O., Seurin, P., Wiggins, J., Pratt, L., Rana, L., Yasaei, R., & Renard, G. (2025). Chapter 9 - Natural Language Processing for Earth resource management: a case of H2 Golden Retriever research. In Data Analytics and Artificial Intelligence for Earth Resource Management(pp 157-183). Elsevier.
• Yasaei, R., & Faruque, M. (2024). Context-Aware Adaptive Anomaly Detection in IoT Systems. In Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing: Use Cases and Emerging Challenges(pp 177--200). Springer Nature Switzerland.

Journals/Publications

• Lin, Y., Ghimire, S., Nandimandalam, A., Camacho, J. M., Tripathi, U., Macwan, R., Shao, S., Rafatirad, S., Yasaei, R., Satam, P., & others, . (2025). LLM-HyPZ: Hardware Vulnerability Discovery using an LLM-Assisted Hybrid Platform for Zero-Shot Knowledge Extraction and Refinement. LLM4Sec 2025, Workshop on the use of Large Language Models for Cybersecurity.
• Yasaei, R., Masuda, A. S., Moghaddas, Y., & Al Faruque, M. A. (2024). Graph Deviation Network for Anomaly Detection and Localization in Additive Manufacturing Systems. ACM Transactions on Cyber-Physical Systems.
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  Additive Manufacturing (AM) has revolutionized industries by enabling the production of complex, customized products with unparalleled efficiency. However, the increasing reliance on AM in critical sectors such as aerospace, healthcare, and defense has exposed it to significant cybersecurity and reliability challenges, including intellectual property theft, process sabotage, and data tampering. These vulnerabilities as well as reliability issues can compromise product integrity, safety, and operational continuity, posing severe risks to both industry and national security. In this work, we propose an novel methodology for modeling the AM process chain as a Cyber-Physical System (CPS) using multi-modal data structured in a graph format. Our methodology leverages Graph Neural Networks (GNNs) to detect and localize anomalies across diverse data modalities, enabling precise identification of both the nature and source of attack/fault. By integrating data fusion, advanced anomaly classification, and localization techniques, our solution provides a robust methodology for enhancing the security and reliability of AM processes, ensuring their safe deployment in critical applications. Furthermore, the proposed technique is adaptable to other industrial systems, underscoring its potential for broader impact in securing critical infrastructure.
• Yasaei, R., Chen, L., Yu, S., & Faruque, M. (2024). Hardware Trojan Detection using Graph Neural Networks. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. doi:10.1109/TCAD.2022.3178355
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  The globalization of the Integrated Circuit (IC) supply chain has moved most of the design, fabrication, and testing process from a single trusted entity to various untrusted third party entities around the world. The risk of using untrusted third-Party Intellectual Property (3PIP) is the possibility for adversaries to insert malicious modifications known as Hardware Trojans (HTs). These HTs can compromise the integrity, deteriorate the performance, and deny the functionality of the intended design. Various HT detection methods have been proposed in the literature; however, many fall short due to their reliance on a golden reference circuit, a limited detection scope, the need for manual code review, or the inability to scale with large modern designs. We propose a novel golden reference-free HT detection method for both Register Transfer Level (RTL) and gate-level netlists by leveraging Graph Neural Networks (GNNs) to learn the behavior of the circuit through a Data Flow Graph (DFG) representation of the hardware design. We evaluate our model on a custom dataset by expanding the Trusthub HT benchmarks trusthub1. The results demonstrate that our approach detects unknown HTs with 97% recall (true positive rate) very fast in 21.1ms for RTL and 84% recall in 13.42s for Gate-Level Netlist.

Proceedings Publications

• Yasaei, R., & Alharthi, D. N. (2025). LLM-Driven Cloud Log Analysis for Threat Detection and Forensics. In IEEE CLOUD 2025.
• Yasaei, R., Moghaddas, Y., & Al, F. (2024). IoT-GRAF: IoT Graph Learning-Based Anomaly and Intrusion Detection Through Multi-Modal Data Fusion. In 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE).
• Yasaei, R., Zargari, A., Al Faruque, M., & Kurdahi, F. (2024). Unraveling Sensor Correlations in Multi-Sensor Wearable Devices for Smart Anomaly Detection. In 2024 IEEE 17th Dallas Circuits and Systems Conference (DCAS).
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  In health monitoring and activity tracking technologies, wearable or implantable sensors have become indispensable, linking various human body regions to collect vital health data. Despite their potential, ensuring the security and reliability of these devices presents significant challenges, primarily due to the complexity of real-world scenarios that these systems encounter. Current approaches often rely on anomaly detection models that process historical sensor data to identify issues. However, these models tend to falter when faced with unexpected conditions or 'corner cases,' lacking the ability to generalize across the diverse situations encountered in everyday use. This limitation is particularly critical in wearable devices, where unexpected incidents are of paramount importance and cannot be overlooked. Addressing this gap, our research investigates multi-sensor wearable systems to understand the context of system operations and their characteristics. We introduce a context-aware approach that leverages the unique physics of the human body to identify the intricate relationships between sensors. By extracting sensor relations and patterns, our approach aims to enhance the detection of security and reliability issues, offering an advancement over traditional methods.

Presentations

• Yasaei, R. (2024). Hardware Security and Semiconductor Workforce Development in the Era of the CHIPS Act. Women in CyberSecurity (WiCyS) conference.
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  This workshop offers a unique introduction to the rapidly evolving field of semiconductor security, a critical area in today’s cybersecurity landscape that has gained even greater relevance under initiatives like the CHIPS Act. As the semiconductor industry faces a growing demand for skilled professionals in security, this workshop provides attendees with foundational knowledge and hands-on experience in protecting hardware components and integrated circuits against emerging threats. Through practical exercises and discussions, participants will explore essential concepts such as hardware trojans, side-channel attacks, secure design principles and verification techniques. This workshop is ideal for students, researchers, educators and professionals interested in semiconductor security, equipping them with the skills and confidence needed to pursue roles in this high-demand domain. It also provides a strong foundation for certifications such as Global Information Assurance Certification (GIAC) Hardware Security Professional (GSEH), supporting the industry’s workforce development goals. This workshop equips both new and existing professionals with the essential skills and knowledge to navigate the evolving landscape of semiconductor security, addressing the pressing workforce needs highlighted by the CHIPS Act and preparing them for impactful roles in this high-demand field.