Tosiron Adegbija

Interests

Research

My research interests include high performance and adaptable embedded computing architectures and optimization methodologies, and right-provisioned microprocessor architectures for the Internet of Things (IoT). Due to the power and thermal constraints that have nearly halted increases in clock speed, coupled with design complexity and scalability issues, microprocessor manufacturers have turned to multicore architectures, where multiple processors are integrated on a single die. Additionally, with the growth of the IoT and consumer demand for mobility, compute- and memory-intensive applications that are currently executed on desktop and server systems must increasingly be executed on resource-constrained systems (e.g., mobile devices, embedded systems, etc.). Significant emphasis must be placed on equipping these systems with the right-provisioned computing resources to support the increasing execution demands. Thus, my research interests include, but are not limited to, dynamic optimizations, low power embedded system design, phase-based tuning, heterogeneous multicore systems, configurable systems, high performance computing, real-time systems, emerging computer architectures, and low-power processors for the Internet of Things (IoT).

Courses

Scholarly Contributions

Journals/Publications

• Limaye, A., Tumeo, A., & Adegbija, T. (2021). Energy characterization of graph workloads. Sustainable Computing: Informatics and Systems, 29, 100465.
• Chaczko, Z., Klempous, R., Rozenblit, J., Adegbija, T., Chiu, C., Kluwak, K., & Smutnicki, C. (2020). Biomimetic Middleware Design Principles for IoT Infrastructures. Acta Polytechnica Hungarica, 17(5).
• Cordeiro, R., Gajaria, D., Limaye, A., Adegbija, T., Karimian, N., & Tehranipoor, F. (2020). ECG-Based Authentication Using Timing-Aware Domain-Specific Architecture. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 39(11), 3373-3384.
• Criswell, K., & Adegbija, T. (2019). A Survey of Phase Classification Techniques for Characterizing Variable Application Behavior. IEEE Transactions on Parallel and Distributed Systems (TPDS).
• Dai, C., & Adegbija, T. (2019). CONDENSE: A Moving Target Defense Approach for Mitigating Cache Side Channel Attacks. IEEE Consumer Electronics Magazine (ISVLSI 2017 Special Issue).
• Kuan, K., & Adegbija, T. (2019). Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).
• Kuan, K., & Adegbija, T. (2019). HALLS: A Highly Adaptable Last Level STT-RAM Cache Architecture. IEEE Transactions on Computers (TC).
• Adegbija, T., & Gordon-Ross, A. (2017). PhLock: A Cache Energy Saving Technique Using Phasebased Cache Locking. IEEE Transactions on Very Large Scale Integration Systems (TVLSI).
• Adegbija, T., & Gordon-Ross, A. (2017). TaPT: Temperature-Aware Dynamic Cache Optimization for Embedded Systems. MDPI Computers Journal, Special Issue on Multi-Core Systems-On-Chips Design and Optimization.
• Adegbija, T., Gordon-Ross, A., & Munir, A. (2014). Phase distance mapping: a phase-based cache tuning methodology for embedded systems. Design Automation for Embedded Systems; Special Issue on Self-adaptive Networked Embedded Systems, 18(3-4), 251--278.

Proceedings Publications

• Kuan, K., & Adegbija, T. (2020). A Study of Runtime Adaptive Prefetching for STTRAM L1 Caches. In 2020 IEEE 38th International Conference on Computer Design (ICCD).
• Adegbija, T., Lysecky, R. L., & Kumar, V. N. (2019, May). Right-Provisioned IoT Edge Computing: An Overview. In ACM Great Lakes Symposium on VLSI (GLSVLSI), Washington DC.
• Gajaria, D., & Adegbija, T. (2019, October). ARC: DVFS-Aware Asymmetric-Retention STT-RAM Caches for Energy-Efficient Multicore Processors. In International Symposium on Memory Systems (MEMSYS), Washington DC.
• Gajaria, D., Kuan, K., & Adegbija, T. (2019, October). SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning. In International Green and Sustainable Computing Conference (IGSCC), Washington DC.
• Hammam Alsafrjalani, M., Adegbija, T., & Ramamoorthi,, L. (2019, March). Evaluating Design Space Subsetting for Multi-Objective Optimization in Configurable Systems. In International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA.
• Kuan, K., & Adegbija, T. (2019, May). MirrorCache: An Energy-Efficient Relaxed Retention L1 STTRAM Cache. In ACM Great Lakes Symposium on VLSI (GLSVLSI), Washington DC.
• Kuan, K., & Adegbija, T. (2019, October). Advancing STTRAM Caches for Runtime Adaptable Energy- Efficient Microarchitectures. In International Green and Sustainable Computing Conference (IGSCC), Washington DC.
• Yazdi, E. T., Limaye, A., Akoglu, A., & Adegbija, T. (2019, December). Bit-wise and Multi-GPU Implementations of DNA Recombination Algorithm. In IEEE International Conference on High Performance Computing, Data, and Analytics (HiPC), Hyderabad, India.
• Pate, J., & Adegbija, T. (2018, January). AMELIA: An Application of the Internet of Things for Aviation Safety. In IEEE Consumer Communications and Networking Conference (CCNC), Las Vegas, NV.
• Adegbija, T., & Tandon, R. (2017, July). Coding for efficient caching in multicore embedded systems. In International Symposium on VLSI (ISVLSI).
• Dai, C., & Adegbija, T. (2017, July). Exploiting configurability as a defense against cache side channel attacks. In International Symposium on VLSI (ISVLSI).
• Gianelli, S., & Adegbija, T. (2017, July). PACT: Priority-Aware Phase-based Cache Tuning for Embedded Systems. In International Symposium on VLSI (ISVLSI).
• Gianelli, S., Richter, E., Jimenez, D., Adegbija, T., & Akoglu, A. (2017, September). Application-Specific Autonomic Cache Tuning for General Purpose GPUs. In IEEE International Conference on Cloud and Autonomic Computing (ICCAC).
• Gianelli, S., Richter, E., Jimenez, D., Valdez, H., Adegbija, T., & Akoglu, A. (2017, September). Application-Specific Autonomic Cache Tuning for General Purpose GPUs. In IEEE International Conference on Cloud and Autonomic Computing (ICCAC), Tucson, AZ, 104-113.
• Limaye, A., & Adegbija, T. (2017, July). A Workload Characterization for the Internet of Medical Things (IoMT). In IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Bochum, Germany.
• Pate, J., & Adegbija, T. (2017, July). AMELIA: a prototype example for edge computing on the Internet of Things. In International Symposium on VLSI (ISVLSI).
• Adegbija, T. (2016, Winter). Exploring Non-Volatile Memory-based Caches for Energy-Efficient Embedded Systems. In ACM Great Lakes Symposium on VLSI (GLSVLSI).
• Adegbija, T., & Gordon-Ross, A. (2016, July). Phase-based Dynamic Instruction Window Optimization for Embedded Systems. In International Symposium on VLSI (ISVLSI).
• Adegbija, T., & Gordon-Ross, A. (2015, Spring). Phase-based Cache Locking for Embedded Systems. In ACM Great Lakes Symposium on VLSI (GLSVLSI).
• Adegbija, T., Rogacs, A., Patel, C., & Gordon-Ross, A. (2015, Spring). Enabling Right- Provisioned Microprocessor Architectures for the Internet of Things. In ASME International Mechanical Engineering Congress & Exposition (IMECE).
• Adegbija, T., & Gordon-Ross, A. (2014). Thermal-aware phase-based tuning of embedded systems. In Proceedings of the 24th edition of the great lakes symposium on VLSI.
• Adegbija, T., & Gordon-Ross, A. (2014, January). Energy-efficient phase-based cache tuning for multimedia applications in embedded systems. In Consumer Communications and Networking Conference (CCNC), 2014 IEEE 11th.
• Adegbija, T., & Gordon-Ross, A. (2014, July). Dynamic Phase-based Optimization of Embedded Systems. In VLSI (ISVLSI), 2014 IEEE Computer Society Annual Symposium on.
• Adegbija, T., Gordon-Ross, A., & Rawlins, M. (2014, 2014). Analysis of cache tuner architectural layouts for multicore embedded systems. In Performance Computing and Communications Conference (IPCCC), 2014 IEEE International.
• Adegbija, T., & Gordon-Ross, A. (2013, October). Exploiting dynamic phase distance mapping for phase-based tuning of embedded systems. In Computer Design (ICCD), 2013 IEEE 31st International Conference on.
• Adegbija, T., & Gordon-Ross, A. (2013, October). Exploring the tradeoffs of configurability and heterogeneity in multicore embedded systems. In Int. Con. on Mobile Ubiquitous Comp., Systems, Services and Technologies (UBICOMM'13).
• Adegbija, T., Gordon-Ross, A., & Munir, A. (2012, October). Dynamic phase-based tuning for embedded systems using phase distance mapping. In Computer Design (ICCD), 2012 IEEE 30th International Conference on.

Presentations

• Adegbija, T. (2020, Fall 2020). The Internet of Things: Overview, Recent Advancements, and Future Trends. Webinar. SRM College of Engineering and Science, India.
• Adegbija, T. (2019, Fall 2019). Architecture Designs for Energy-Efficient and Adaptable STTRAM Cache Hierarchies. National University of Singapore. National University of Singapore.
• Adegbija, T. (2019, Fall 2019). Emerging Technologies for Right-Provisioned IoT Computing. Panel Session at ACM Great Lakes Symposium on VLSI (GLSVLSI). Washington, DC, USA.
• Adegbija, T. (2019, Fall). Emerging Technologies for Right-Provisioned IoT Computing. Panel Session at ACM Great Lakes Symposium on VLSI (GLSVLSI); Washington DC.
• Adegbija, T. (2019, October). Architecture Designs for Energy-Efficient and Adaptable STTRAM Cache Hierarchies. National University of Singapore.
• Adegbija, T. (2018, May 2018). Potentials of Microarchitecture Adaptability for Performance, Energy, and Security Optimizations. Emerging Technologies Conference (ETCMOS). Whistler BC, Canada.
• Adegbija, T. (2018, Summer 2018). Academic Career Challenges. Panel Session at Design Automation Conference (DAC) Early Career Workshop. San Francisco, CA USA.
• Adegbija, T. (2018, Summer 2018). Attacking Dynamic Optimizations in the Era of Complex Heterogeneous Multi-core Computing. Special Session Organized at IEEE Computer Society Symposium on VLSI (ISVLSI). Hong Kong.